1. Field of the Invention
The present invention relates to a semiconductor memory having transistor cells each of which stores multiple bit data, and a method for manufacturing such semiconductor memory.
2. Description of Background Art
A nonvolatile semiconductor memory such as a flash memory is widely applied to electronic appliances like a mobile telephone. In order to promote size reduction and larger information capacity of the electronic appliances, it is required to miniaturize the semiconductor memory and increase the storage capacity of the semiconductor memory. Thus, there should preferably be implements the multiple-bit configuration of a cell transistor that allows two or more bit data to be stored in a single cell transistor. The nonvolatile semiconductor memory described in US 2004/0169219 A1, filed by the assignee of the present application, has cell transistors each of which comprises a pair of floating gates that are electrically isolated and stores two bits (four values) of information.
FIG. 54 shows a conventional cell array (memory cell array) 100 that has plural bit lines BL extending in a column direction, plural word lines WL extending in a row direction, and electrically isolated floating gates FG1, FG2 that are formed in the intersected area between the bit line BL and the word line WL. The cell transistor 101 is formed in an encircled area of FIG. 54 in which the bit line BL and the word line WL are intersected.
In FIG. 55, the sectional view of the cell transistor 101 taken on the line D-D of FIG. 54 is illustrated. The cell transistor 101 comprises a control gate CG (word line WL), a pair of diffusion regions 102 that serves as the source and the drain. When the control gate CG, the source and the drain regions are supplied with predetermined voltages, a channel is generated in the top and side surfaces of a projection 104 that is formed on a silicon substrate 103. In data writing operation of the cell transistor 101, some electrons (charged particles) in the channel are supplied with enough energy to become hot electrons that can pass the potential barrier in a first insulation layer 105 and flow into a drain side floating gate. In data reading operation to read the information from the cell transistor 101, the electric current flowing in the channel (drain current) is modulated in accordance with the amount of the electrons in the source side floating gate. In deleting the information in the cell transistor 101, there is no channel in the projection 104, and the electrons in the floating gates FG1, FG2 are discharged to the control gate CG through a second insulation layer 106 by FN (Fowler Nordheim) tunneling.
As illustrated in FIG. 54, the width in the column direction of the floating gates FG1, FG2 is equal to the width of the word line WL. Such floating gates FG1, FG2 are formed by patterning the word lines WL, and by patterning the conductive material for the floating gate covered with an insulation layer. In the patterning process of the conductive material, the insulation layer on the word line WL serves as the hard mask. In other words, the floating gates FG1, FG2 are formed by the self-align process in the column direction with respect to the word lines WL.
In forming the floating gates FG1, FG2 by the self-align process, it is required to etch a portion of the insulation layer covering the conductive material for the floating gate to expose the surface of the conductive layer, and then to etch the conductive material. In etching the insulation layer covering the conductive material, the insulation layers 105-107 are damaged. Such cell transistor 101 with the damaged insulation layers 105-107 becomes less reliable in operation. As described so far, the self-align process to form the floating gates and the word lines (control gates) still has some problems, so it is desired to solve the problems